1. Field of the Invention
The present invention relates to a semiconductor memory device which is a so-called multi-port SRAM (Static Random Access Memory) having a holding circuit (flip-flop circuit) and a read output circuit which outputs a signal corresponding to data held by the holding circuit.
2. Description of the Related Art
SRAMs include memory cells arranged horizontally and vertically and each memory cell has a holding circuit for holding memory data. Memory cells included in a multi-port SRAM each have, for example, a read-only output circuit so that read can be simultaneously performed with respect to a plurality of memory cells or read and write can be simultaneously performed. Japanese Unexamined Patent Application Publication No. 2002-43441 (FIGS. 8 and 9) discloses an example of the above-described SRAM having a circuit configuration of memory cells each including write access transistors (N3, N4) and, in addition, a read drive transistor (N8) and a read access transistor (N9), and a layout of the transistors and the like. Each of these transistors has the same gate length as that of a transistor included in the holding circuit.
There is a known SRAM which has a hierarchical bit line structure so as to increase access speed. Japanese Unexamined Patent Application Publication No. 2004-47003 and U.S. Pat. No. 6,014,338 discloses an SRAM which includes a plurality of local read bit lines and a single global read bit line and in which each memory cell is connected to a corresponding one of the local read bit lines. In such an SRAM, the length of the local read bit line can be suppressed to a small quantity, so that the parasitic capacitance can also be suppressed to a small quantity, thereby making it possible to easily achieve high-speed access.
In the above-described multi-port SRAMs, when a plurality of columns in each of which memory cells are arranged in a direction along the bit line are arranged in a direction perpendicular to the bit line, erroneous read is likely to occur. For example, in the above-described SRAMs, two memory cells belonging to the same row may be simultaneously selected for write and read. In this case, in the read memory cell, since a write access transistor goes to the ON state, the potential of an I/O node of the holding circuit varies depending on the potential of a write bit line. Therefore, the potential of a read bit line is also affected, so that erroneous read is likely to occur.
In the SRAM having the hierarchical bit line structure, a global read bit line is provided for each column. If the potentials of the global read bit lines all vary depending on signals read from memory cells in the respective columns, power is consumed corresponding to changes in the potentials.